FIFO interface
英
美
【计】先进先出接口
双语例句
- The BlockingQueue interface states that it is a Queue, meaning that its items are stored in first in, first out ( FIFO) order.
BlockingQueue接口表示它是一个Queue，意思是它的项以先入先出（FIFO）顺序存储。 - Realization of FPGA Expanding FIFO Based on the Interface Chip of PCI
基于PCI接口芯片外扩FIFO的FPGA实现 - The asynchrony FIFO module can be applied in the other asynchrony interface circuit design in multi-clock system.
异步FIFO的设计方案对于多时钟系统中异步接口电路的设计具有一定的参考价值。 - Furthermore, the control logic circuit and FIFO memory are integrated into the FPGA, improving the stability and integration of the system. It is an advanced data acquisition and control interface for the new generation patch clamp system.
而且在大规模可编程逻辑器件内实现了控制逻辑电路和FIFO存储器，提高了系统的集成性和工作稳定性，是比较理想的新一代膜片钳系统数据采集系统。 - The scheme is based on ARM and FPGA with high-speed AD and FIFO, in which the interface to virtual instruments is implemented with USB, the interface to intelligent instruments implemented with graphic LCD, and the virtual interface implemented with Delphi.
该方案基于ARM和FPGA，配合高速AD和FIFO，以USB实现虚拟仪器接口，以图形液晶LCD实现智能方式仪器界面，用Delphi实现虚拟界面。 - FIFO Data Interface Between Clock Systems Inside FPGA
FPGA内部时钟系统间的FIFO数据接口 - The peripheral controller consists of frequency detector, data sample controller, FIFO, LCD driver and the interface circuit between DSP and FPGA.
外围控制器囊括了硬件系统中几乎所有的数字电路，包括频率/周期测量、数据采集控制、FIFO、LCD驱动以及FPGA与DSP之间的接口电路等。 - The design of PCI bus on FIFO chip from hardware solve the problem of frequent calling system interrupt in data high-speed interchange, which will be of great benefit for the application and development of PCI interface.
基于FIFO芯片来实现PCI插卡，从硬件上解决了数据高速交换中频繁调用系统中断的问题，对PCI接口的应用与推广大有益处。 - The interface uses a circuit based on dual port FIFO buffer memory to realize data transfer of different I/ O velocity between the two computers.
该接口采用双端口FIFO缓冲存储技术，实现两机间不同I／O速度的数据通信。 - The data encrypt card using DSP chip, PCI interface chip, asynchronism FIFO chip and EPLD that realize the control of the data encrypt card is designed and implemented.
数据加解密卡的硬件设计和实现。采用DSP芯片、PCI接口芯片、异步FIFO等器件，通过EPLD控制实现了数据加解密卡； - In practice, this paper gives a detailed design implementation of various UART modules including reciever/ transmitter, baud-rate generator, synchronous FIFO ( First In First Out), Modem control module, interface module.
在具体实现上，本文给出了UART的各个模块的详细设计，包括：发送器、接收器、波特率发生器、同步先进先出缓存（FIFO：FirstinFirstout）、Modem控制模块、接口模块。 - In the paper, we especially introduced the hardware architecture, signal conditioning, A/ D conversion, FIFO circuit, USB interface circuit and EZ-USB firmware, application program and driver. It has extensive application foreground.
该文对系统硬件结构、信号调理、A/D转换、FIFO缓存和USB接口电路，以及EZ-USB的固件程序、PC端的应用程序和USB设备驱动程序进行了阐述，具有广阔的应用前景。 - The hardware mainly determines the interface circuit between the MCU, USB 2.0 chip and FIFO. The system software can be divided into three modules. The first is the device firmware program by Keil C.
硬件设计主要解决的是MCU、USB2.0接口芯片和FIFO之间的接口电路问题，系统软件分为三个模块：一是采用keilC语言编写的设备固件程序； - The application of network router shows that the asynchronous FIFO interface based of Gray code can solve the problem of clock domain switching pithily and efficiently.
经过在网络路由器的应用表明，基于Gray码的异步FIFO接口能够简洁、高效的解决时钟域切换的问题。 - The hardware is made up by the signal conditioning circuits, the A/ D converting module, the FIFO buffering circuits, the PCI interface, the FPGA control circuits and peripheral circuits.
硬件部分主要由信号预处理电路，A／D转换模块、FIFO缓存电路，PCI总线接口电路，FPGA控制电路及外围电路组成。 - Design of Interface Card of CAN Bus with FIFO
采用FIFO的CAN总线接口卡的设计 - According to the characteristics of control and data transfer in data collect system, a general USB interface system is designed which is based on FIFO.
针对数据采集系统控制和数据传输的特点，设计了基于FIFO的通用USB接口。 - This paper introduced parallel communication methods of multiple monolithic computers with shared FIFO components. Here, the design of parallel communication interface of multiple monolithic computers system that use inquiry and interrupt method is mainly presented.
共用FIFO器件的多单片机系统并行通信方法，主要介绍采用查询方式和中断方式的多单片机系统并行通信接口设计。 - Moreover, as real-time collection and analysis can produce large interface flow, we used memory pool and FIFO storage to improve the processing efficiency of the platform.
另外由于进行实时的采集分析，接口流量大，使用了内存池和FIFO存储器方法改善平台的处理效率。 - As a slave device, the IP core includes AXI interface, two non-symmetrical FIFO, DMA interface and AES encryption core.
AES核做为SoC系统中的从设备，整个IP核包含了AXI接口，两个非对称FIFO与DMA接口，以及AES加解密核。 - The hardware circuit includes ultrasonic excitation emission circuit, ultrasonic amplitude limiting circuit, ultrasonic amplifying and filtering circuit, detection circuit, A/ D circuit, FIFO circuit, SCM control circuit and interface circuit.
硬件电路主要包括超声激励发射电路、超声限幅电路、超声放大滤波电路、超声检波电路、A/D电路、FIFO电路、单片机控制电路以及接口电路。